In general, current memory designs place static random access memory (SRAM) blocks and read only memory (ROM) blocks into completely separate arrays. These arrays then are not physically in proximity with each other and do not share the same basic cell layout. As a result of this, such SRAM blocks and ROM blocks typically have separate address decoding circuitry, output sensing and multiplexing circuitry, and timing circuitry. Some common adverse consequences of this are increased overall circuit complexity, footprint, and power consumption and dissipation.
Designs have now appeared where SRAM and ROM blocks use either common address decoding circuitry or shared sense amplifiers. Relatively recently, a few designs unify SRAM and ROM blocks in physical proximity in the same basic cell layout. These early unified designs, however, still have a number of disadvantages.
For example, U.S. Pat. No. 6,826,073 by Liaw et al. (hereinafter Liaw '073) teaches a combination cell that adds a seventh-transistor ROM circuit to an essentially conventional six-transistor SRAM circuit. The result here, unfortunately, has a number of limitations. For instance, the resulting memory cell has a single word line; a bit line and a bitnot line for its SRAM function (i.e., the conventional differential arrangement); and yet further has a third bit line for its ROM function. When the single word line of Liaw '073 is enabled both its SRAM and ROM functions are accessed together, and the storage states of both appear across the three bit lines. It then falls upon “down stream” circuitry that is necessarily provided and used here to sort out whether RAM or ROM has been read.
Another example of a unified bit cell design is seen in U.S. Pat. No. 6,128,218 by You et al. (hereinafter You '218). This teaches a hybrid memory device that includes an essentially conventional six-transistor SRAM circuit and a four-transistor ROM circuit. [You '218 also teaches a six-transistor SRAM and six-transistor 2xROM cell that is not relevant here.] Conforming with tradition, and thus unlike Liaw '073, You '218 employs only a differential bit and bitnot line arrangement for both its SRAM and ROM functions. For its SRAM function You '218 employs a RAM word line, but for its ROM function it employs both a ROM word line and a ROM activation line. Thus, You '218 uses at least twice the transistors that are used in conventional two-transistor ROM cells, and using cells of this type requires complex “up stream” address decoding circuitry.
Accordingly, there still remains a need for a unified SRAM/ROM cell that efficiently integrates physically into a same basic cell layout, without increasing the transistor count beyond that of discrete SRAM cell and ROM cell solutions, and that uses simple and essentially conventional bit and word line arrangements.